The present disclosure relates to a semiconductor memory device, and more particularly, to a precharge control circuit.
FIG. 1 illustrates a circuit diagram of a conventional precharge circuit for precharging local input/output lines LIO. FIG. 2 illustrates a circuit diagram of a conventional precharge control circuit. FIG. 3 illustrates a timing diagram of the conventional precharge control circuit of FIG. 2.
Referring to FIG. 1, in a conventional precharge circuit 100, a signal LIORST is set to a logic high level during a burst operation to perform a write or read operation. After a write or read operation for a first address, the signal LIORST is set to a logic low level to precharge the local input/output lines LIO. Thereafter, the signal LIORST is again set to the logic high level during a next burst operation to perform a write or read operation, and the precharging of the local input/output lines LIO is repeated until the burst operation is ended.
However, in a case where the write operation is repeated, a precharging operation is not required because data is input from an external source to strongly drive a write driver. Meanwhile, in a case where the read operation is repeated, the precharging operation is necessary because the local input/output lines LIO are sensed with a small voltage difference.
Referring to FIG. 2, in order to avoid an unnecessary precharging operation, a conventional precharge control circuit uses a signal WTRDB to precharge the local input/output lines LIO during only a read operation, not precharging local input/output lines LIO during a write operation. The signal WTRDB is set to a logic high level during a write operation and to a logic low level during a read operation. The signal WTRDB is NANDed with a signal TM_WTNOPCG. The resultant NANDed signal can be controlled by a test mode signal.
A control signal WTNOPCG output in this manner is NORed with a signal LIO_RST to generate a signal LIO_RST_RD for precharging the local input/output lines LIO.
Referring to FIG. 3, the signal LIO_RST_RD is maintained at a logic high level during a write operation. Thus, the conventional precharge control circuit performs a precharge operation only during a read operation, without performing a precharge operation during the write operation.
In this instance, the circuit can be easily changed using the existing signal WTRDB. However, as illustrated in FIG. 3, a sufficient timing margin may not be provided at a point T2 at which the write operation is switched to the read operation, and a high voltage and a high-frequency clock may cause an error in the precharging operation.